1. Field of the Invention
This invention relates to integrated circuit manufacture and more particularly to a method of manufacturing wafer slice starting material which incorporates an extrinsic gettering technique.
2. Description of the Relevant Art
Methods of gettering a silicon substrate are well known. Gettering is used to remove lifetime reducing contaminants (usually heavy metals) from regions of the circuit where their presence would degrade device performance. Most all the transition metals, such as gold, copper, iron, titanium, nickel, etc., are reported as possible lifetime reducing contaminants. It is desirable to reduce the presence of such contaminants in the active regions in order to reduce reverse junction leakage, improve bipolar transistor gain, and increase refresh time in dynamic metal oxide semiconductor (MOS) memories.
Lifetime reducing contaminants (heavy metals) may be introduced into a semiconductor substrate in a number of ways. First, heavy metal contaminants may be derived from processing equipment during wafer fabrication. For example, delivery lines are often made of stainless steel. Thus heavy metal atoms comprising stainless steel species may be introduced into a semiconductor substrate during wafer fabrication. The semiconductor substrate may also receive heavy metal ions during diffusion, ion implantation, chemical vapor deposition (CVD), plasma etching, and sputtering operations.
Second, heavy metal atoms are often derived from the conductive material placed on the frontside and backside surfaces of a semiconductor substrate. Frontside surface conductive material, generally referred to as "metallization", inherently uses heavy metal materials such as titanium and tungsten to enhance silicide growth and interconnect conductivity. A coating of gold is typically placed on the backside surface of a semiconductor substrate during the final stages of device fabrication to provide power supply conductivity to the semiconductor substrate, and also as an aid to bonding of the backside surface to the chip package. Heavy metals placed on the frontside and backside surfaces may migrate to the active regions and deleteriously effect circuit operations.
Gettering within the bulk of a semiconductor substrate is typically used to trap contaminants such as heavy metals at sites away from device active regions. There are two common forms of gettering: intrinsic gettering and extrinsic gettering.
Intrinsic gettering involves forming gettering sites in the bulk of a semiconductor substrate, generally below the active regions near the frontside surface of the semiconductor substrate. In silicon substrates (wafers) manufactured using the Czochralski (Cz) method, intrinsic gettering generally includes an initial denuding step (for wafers without silicon epitaxial layers) followed by a nucleation step, and then a precipitation step. Denudation, nucleation, and precipitation, in combination, form lattice dislocations in the silicon bulk below the active regions. The dislocations serve to trap heavy metal ions at the dislocation sites, away from the overlying active regions.
Extrinsic gettering, on the other hand, generally involves gettering near the backside surface of a silicon substrate. There are several methods used to perform extrinsic gettering. Two common methods include (i) diffusing phosphorous into the backside surface of a silicon wafer, and/or (ii) depositing polycrystalline silicon (polysilicon) on the backside surface of a silicon wafer. Diffusion processes utilizing extrinsic gettering techniques such as backside phosphorous diffusion and polysilicon deposition is described in Runyan, et al., Semiconductor Integrated Circuit Processing Technology, (Addison-Wesley Publishing Co., 1990), pp. 428-442; and, DeBusk, et al., "Practical Gettering in High Temperature Processing", Semiconductor International, (May 1992) (both of which are herein incorporated by reference).
Extrinsic gettering is the subject of this application. Deposited doped polysilicon has become the standard gate electrode material for MOS transistors. In common silicon gate MOS processes, a gate polysilicon layer is deposited over a gate oxide layer early in the device fabrication process. An extrinsic gettering technique may take place before gate polysilicon is deposited, or may be combined with wafer fabrication steps after gate polysilicon deposition. As defined herein, initial semiconductor fabrication occurs prior to deposition of a layer of gate polysilicon. On the other hand, process-induced (or "in-process") extrinsic gettering techniques are combined with standard wafer fabrication operations which occur after gate polysilicon deposition.
Gettering techniques employed during initial semiconductor fabrication are potentially more effective than in-process techniques. Gettering sites produced during initial semiconductor fabrication have an opportunity to trap mobile contaminants away from the active device areas of the frontside surface of the silicon substrate before the wafer is subjected to any contaminants arising from normal processing flow. Any contaminants brought about by the process tool, or by operator involvement, will be obviated by the presence of pre-existing gettering sites.
Current backside surface phosphorous diffusion techniques involve placing silicon wafers on-edge in a wafer boat, and inserting the wafer boat into a diffusion furnace containing n-type dopants (i.e., phosphorous). Thus both the frontside and backside surfaces of silicon wafers are subjected to phosphorous ions in a diffusion furnace.
It is well known that "outgassing" of phosphorous impurities, introduced into the backside surface of a silicon wafer in an extrinsic gettering process, may contaminate active device regions on the frontside surface during subsequent processing steps such as thermal oxidation.
In common silicon gate MOS processes, phosphorus backside gettering is typically incorporated into wafer fabrication following deposition of the gate polysilicon layer over the gate oxide layer. The phosphorus, diffused into both the frontside and backside surfaces of the wafer, may thus provide extrinsic gettering at the backside surface as well as lower the electrical resistivity of the polysilicon layer at the frontside surface. The deleterious effects of any outgassing of phosphorus atoms from the backside surface during subsequent thermal processing steps are thus mitigated.
As with diffusion, conventional oxidation and polysilicon deposition processes typically involve placing silicon wafers on-edge in a wafer boat. Silicon wafers in the wafer boat may then be subjected to an oxidation or polysilicon deposition process. Thus both the frontside and backside surfaces of silicon wafers are simultaneously subjected to the same oxidation, or polysilicon deposition process ambient.
In a wafer fabrication process employing a process-induced extrinsic phosphorus gettering technique, phosphorus diffusion may occur after gate oxide growth and gate polysilicon deposition. During the gate oxide growth and gate polysilicon deposition processes, oxide and polysilicon layers are commonly formed on both sides of a silicon wafer. Gate oxides are typically about 100 angstroms thick. Phosphorous ions, however, cannot easily diffuse through an oxide layer more than about 70 angstroms thick. For this reason, any gate oxide and polysilicon layers deposited prior to phosphorus diffusion must be removed from the backside surface of a silicon wafer so that the backside silicon surface can receive backside phosphorous gettering.
A protective masking material must be placed on the frontside surface of a silicon wafer in order to remove the polysilicon and underlying gate oxide on the backside surface. The protective masking material (e.g., polymerized photoresist) prevents wet etch removal of the underlying polysilicon at the frontside surface of the silicon wafer while allowing removal of exposed polysilicon and gate oxide on the backside surface. Following the stripping of the photoresist from the frontside surface, a hydrofluoric acid solution is then used to remove the gate oxide layer from the backside surface of the silicon wafer.
The above steps of coating the frontside surface of a silicon wafer with photoresist, baking the photoresist, removing polysilicon, photoresist and oxide on the backside surface is not only time consuming, but also involves numerous expensive and caustic materials. Additionally, use of photoresist during early stages of wafer processing may reduce the effectiveness of subsequent photolithography and selective polysilicon removal. Still further, any additional use of photoresist should be avoided in a cleanroom environment since photoresist, and the removal thereof, is a relatively "dirty" procedure which can compromise cleanroom integrity.
It would thus be advantageous to provide an extrinsic gettering technique that may be employed during initial semiconductor fabrication, prior to high-temperature thermal cycles such as anneals which may increase the mobilities of contaminants. Not only would the steps of removing polysilicon and gate oxide from the backside surface of a wafer be eliminated, but the steps of coating the frontside surface with photoresist, baking the photoresist, and removing the photoresist would also be eliminated.